The present invention relates to novel interconnect semiconductor structures and, in particular to a method for improving the adhesion of an inorganic barrier film such as Si3N4 to the copper lines or vias of such interconnect structures. The improved adhesion is obtained in the present invention by treating the copper (Cu) lines or vias in a reducing plasma atmosphere under conditions such that a new material layer comprising Cu, Si, O and optionally at least one of C, H, N and F is formed and thereafter forming the inorganic barrier film on the new material layer. The term xe2x80x9cinterconnect structurexe2x80x9d is used broadly herein to include any semiconductor structure which contains copper interconnect metallurgies. Thus, the present invention is applicable for use in damascene structures (single and dual), memory cell capacitors and other wiring applications for logic, memory and input/output applications.
In the semiconductor industry, aluminum and aluminum alloys have been used as the traditional interconnect metallurgies. While aluminum-based metallurgies have been the material of choice for use as metal interconnects over the past years, concern now exists as to whether aluminum will meet the demands required as circuit density and speeds for semiconductor devices increase. Because of these growing concerns, other materials have been investigated as possible replacements for aluminum-based metallurgies.
One highly advantageous material now being considered as a potential replacement for aluminum metallurgies is copper. This is because copper exhibits a lower susceptibility to electromigration failure as compared to aluminum as well as a lower resistivity.
Despite these advantages, copper readily diffuses into the surrounding dielectric material during subsequent processing steps. To inhibit the diffusion of copper, copper interconnects are often times capped with a protective barrier layer. One method of capping involves the use of a conductive barrier layer of tantalum or titanium, in pure or alloy form, along the sidewalls and bottom of the copper interconnection. To cap the upper surface of the copper interconnection, a dielectric material such as silicon nitride, Si3N4, is typically employed.
Due to the need for low temperature processing after copper deposition, the silicon nitride layer is deposited at temperatures below 450xc2x0 C. Accordingly, silicon nitride deposition is typically performed using plasma enhanced chemical vapor deposition (PECVD) or high density plasma chemical vapor deposition (HDPCVD) wherein the deposition temperature generally ranges from about 200xc2x0 to about 500xc2x0 C.
PECVD and HDPCVD silicon nitride have been used for many other applications in semiconductor device manufacturing. However, in using a silicon nitride cap for copper interconnects, conventional PECVD or HDPCVD silicon nitride creates reliability problems. In particular, silicon nitride films deposited using conventional PECVD or HDPCVD processes generally exhibit poor adhesion to the copper surface. For instance, some nitride films delaminate and form blisters over patterned copper lines, particularly during subsequent dielectric depositions, metallization, and chemical-mechanical polishing.
These results are indicative of how the silicon nitride film might adhere to the copper in actual fabrication processes. After being deposited onto copper metallurgy, additional insulating layers generally will be deposited over the silicon nitride film. However, subsequent deposition of insulating layers onto the nitride film will produce stress which can cause the silicon nitride film to peel from the copper surface. This delamination results in several catastrophic failure mechanisms including: lifting intermetal dielectrics, lifting copper lines, and copper diffusion from uncapped copper lines. Such results are generally seen in dual damascene processing wherein delamination of the silicon nitride RIE stop layer generally occurs during copper chemical-mechanical polishing (CMP).
Prior art nitride to copper adhesion requires siliciding the copper surface by reacting it with silicon. This prior art method has two drawbacks: increases the copper sheet resistance due to silicon reacting with copper and diffusion therein; and marginal nitride to copper adhesion due to incomplete or partial copper silicide formation.
In view of the drawbacks mentioned with prior art copper interconnect structures, there is a continued need to develop a new process of facilitating the adhesion of an inorganic barrier film to copper surfaces which are present on interconnect semiconductor structures.
One object of the present invention is to provide a method of improving the adhesion of an inorganic deposited barrier film to a copper surface of an interconnect structure.
Another object of the present invention is to provide a method whereby the deposited inorganic barrier film does not delaminate from a copper surface of an interconnect structure during subsequent interconnect processing steps.
A further object of the present invention is to provide a method which can be used in dual damascene processing to improve the adhesion of a Si3N4 etch stop layer to copper wiring or copper vias.
A yet further object of the present invention is to provide an interconnect structure in which a material layer comprising Cu, Si, O and optionally at least one of C, H, N and F is formed between the copper lines and vias and the inorganic barrier film.
These and other objects and advantages can be achieved in the present invention by utilizing a method which includes a step of exposing a layer of copper in an interconnect semiconductor structure to a reducing plasma prior to forming an inorganic barrier film on the copper interconnect structure. The reducing plasma treatment is conducted under conditions such that a new material layer is formed on the surface of the Cu lines or vias. The new material layer which comprises Cu, Si, O and optionally at least one of C, H, N and F aids in improving the adhesion of an inorganic barrier film to a Cu line or via. The new material layer formed by the plasma treatment step of the present invention has a thickness that is less than 10 nm.
Specifically, the method of the present invention, which improves the adhesion of an inorganic deposited barrier film on copper surfaces of an interconnect structure, comprises the steps of:
(a) exposing an interconnect semiconductor structure containing at least a layer of copper to a reducing plasma under conditions such that a new material layer comprising Cu, Si, O and optionally at least one of C, H, N and F is formed on said layer of copper; and
(b) forming an inorganic barrier film on said new material layer.
In accordance with the method of the present invention, the exposure step, step (a), is carried out in a plasma comprising at least one non-oxidizing gas selected from the group consisting of H2, N2, NH3, noble gases such as He, Ne, Ar, Kr and Xe, and mixtures thereof. It is noted that oxidizing ambients are excluded from the present invention since the may cause the copper present in the interconnect structure to oxidize and weaken the nitride at the copper interface.
In accordance with another aspect of the present invention, novel interconnect structures are provided. The novel interconnect structures of the present invention comprise at least one copper line or via; a material layer comprising Cu, Si, O and optionally at least one of C, H, N and F formed on said at least one copper line or via; and an inorganic barrier film formed on said material layer.
A highly preferred interconnect structure of the present invention is one wherein the material layer is formed between copper lines or vias and a Si3N4 inorganic barrier film; Si3N4 and Cu usually do not have good adhesion due to poor chemical bonding between the same. In this embodiment, the material layer contains Cu, Si, O and N. The presence of this material layer between the Cu metal and Si3N4 layer greatly improves the adhesion, i.e. chemical bonding, of these two unreacted materials.
Suitable interconnect structures that are contemplated in the present invention include, but are not limited to: memory cell capacitors including plate capacitors, crown capacitors, stack capacitors and other like capacitors; damascene structures including single and dual; multiple wiring levels containing a plurality of vias and metal lines; and other like interconnect structures.